ROM devices, constructed by arranging semiconductor circuit elements in a matrix form, have been widely used as integrated circuits. Prior art ROM devices comprise a plurality of word lines and a plurality of bit lines which are arranged in rows and columns to form a matrix, with gate elements included at selected cross-points of the matrix. Each gate element has first and second electrodes and a control electrode, the control electrode being connected to an associated word line, and the first and second electrodes being connected to an associated bit line and a first potential source, respectively. The bit lines are connected via respective load elements to a second potential source.
In such a ROM device, a write-on operation is performed by selectively arranging the elements at the cross-points. More particularly when a word line is energized at a predetermined selection level, the resistance between the associated bit line and the potential source becomes low at the cross-point provided with the gate element but the resistance remains high at the cross-point without the gate element. While the word line is at a non-selection level, either cross-point remains at an insulating state, so that by selectively activating a word line, read-out outputs can be obtained from the junction points between the associated bit lines and the load elements. Such a ROM device is disclosed, for example, in "MOS/LSI Design and Application" published by McGraw-Hill Book Co., authored by William N. Carr and Jack P. Mize, 1972, pp. 197-198, in which MOS transistors are used as gate elements and load elements.
In prior art ROM devices, the potential of the bit line can be quickly varied via the gate element having a low resistance. The bit line potential will approximate the potential of the first potential source when the gate element is conducting. However, when this gate element assumes a non-selection state, the potential of the bit line is charged to the potential of the second potential source via the load element having a relatively high resistance. Due to the high-resistance load element a long time is required for the charging process. The result is that preparation time is required between a read-out operation and a subsequent read-out operation with the required preparation time being equal to the aforementioned time necessitated for the charging process. Accordingly, the operation speed of the ROM is adversely decreased. In addition, in such a ROM, the memory element and the load element serve as a D.C. current path established between the first and second potential sources during read-out operations. Due to the existence of this current path the ROM has the disadvantage of large power consumption.
It is therefore an object of the present invention to provide a ROM device that can operate at high speeds.
It is a further object of the present invention to provide a ROM that has small power consumption.